The present invention relates to a method and computer architecture for parallel execution of programs on multiple processors.
Computer interrupts are signals received by a computer processor that cause the processor to switch from a current execution task or thread to a different execution task or thread (the latter, for example, being an interrupt service routine) typically as designated by an interrupt identifier. The interrupt service routine executed after the interrupt “handles” the interrupt, after which, the former task is resumed.
Interrupts can be generated by hardware or software. Hardware interrupts let a processor respond to external events (for example, the expiration of a timer) without the need for the processor to periodically check for the event in a “polling” operation. Software interrupts may be triggered by a special instruction executed by the processor. Interrupts may be triggered by errors in the execution of an instruction, for example a division by zero, or by other execution faults such as lack of available memory. These latter interrupts are often called exceptions.
Precise interruptability is provided by a processor if the interrupted thread may be resumed without disruption. Precise interruptability generally requires that the architectural state of the processor be well defined at the time of the interrupt so that this architectural state may be restored when the interrupt has been handled. The architectural state captured at the time of the interrupt should reflect completion of all the instructions preceding the interrupted instruction and none of the succeeding instructions.
Precise interruptability is crucial to a variety of system applications including debugging and resource management, and has allowed innovative micro-architectural techniques, such as speculation, a technique that allows the processor to execute instructions past the point of unresolved branch instructions, for example, by predicting how the branch instruction will be resolved. The need to provide for precise interruptability is likely to grow more important as system exceptions caused by transient processor errors grow more common as the limitations of technology are approached. These latter exceptions, which will be termed transient exceptions, are generally independent of the particular instructions being executed, but are driven by sporadic occasional hardware faults caused, for example, by overheating of the circuitry.
While precise interruptability is a common feature of single processors, it is difficult to achieve in parallel processing environments. Parallel processing uses multiple processors which each may simultaneously execute different portions of a program. Unfortunately, the independent operation of these multiple processors results in a complex and distributed architectural state that is difficult to capture on an instantaneous basis. Without an ability to capture architectural state, precise interruptability cannot be obtained, and advantages of precise interruptability are unavailable.